A Modeling method for Reconfigurable Processor Performance Analysis

Coarse grained reconfigurable architecture (CGRA) has become an important solution for high performance computing because of its high speed up ratio for computation intensive applications, fast configuration, good adaptability and low power consumption. However, the traditional performance analysis method of register transfer level modeling is simulating, which is still widely used. To overcome the shortage of traditional performance analysis method in flexibility and efficiency, we propose a novel method for reconfigurable processor performance analysis based on transaction-level dataflow graph (DFG). This method combined application data flow graph with architectural characteristics through constructing the transaction-level dataflow graph of reconfigurable processor and labeling hardware performance parameters corresponding to functional properties. Using the breadth first search algorithm based on hierarchical search to analysis the tree-like transaction-level dataflow graph, we can get the performance of reconfigurable processor running applications. Experimental results show that the proposed method calculates the performance of reconfigurable processor quite accurately, and benefits the optimization design of architecture and design space exploration.